Book E Architecture - Built For 64-bit processing

Since the announcement last week of IBM's upcoming 64-bit PowerPC processor technology introduction, scheduled for October of this year, the Macintosh audience has been champing at the bit to determine if Apple has plans to use this chip in future Macintosh computers. Apple, of course, will never comment on any future plans, but those who know the company well will tell you that if the new 64-bit PowerPC chip has promise, Apple would naturally consider it.

One of the long-standing technical road maps for the Power Macintosh has been that Apple would follow the PowerPC road maps set out by the AIM Alliance, advancing from the G2 (PowerPC 604e), to the G3 (IBM 750xx currently in the iBook), then to the G4 (Motorola's various 7xxx chips), and forward to the G5 and G6 processor families. The mythical G5 was always meant to be the 32-64-bit transition point, as many PowerPC road maps attest.

Back in May of 1999, Motorola and IBM decided to co-write the Book E architecture for the PowerPC, the purpose of which was to unify their PowerPC architecture plans for the benefit of customers. Book E was said to be planned for the G5 generation of processors and, more importantly to the discussion herein, to provide 84 new instructions for 64-bit addressing.

The AltiVec Question

As an EETimes article makes note of, "Book E defines ways that application-specific processing units (APUs) can be linked to a PowerPC processing core. The AltiVec PowerPC vector processing unit and instructions would be [considered] an APU under the Book E definition."

Back then IBM was asked if they would implement an AltiVec-enabled processor (having been granted a license to AltiVec by Motorola) and the company would not speculate whether they would or not. Apparently IBM has developed their own vector processing instruction set similar to AltiVec, but this does not preclude utilizing AltiVec in some versions of the chip. Treated as an APU in a Book E Architecture chip, AltiVec and IBM's vector processing unit could be swapped into the design for different customers.

Technical Notes

One EETimes article from last year describes the new IBM chip as a "1-GHz plus multicore superscalar processor [which] will incorporate a single-instruction, multiple-data engine along the same lines as Motorola's AltiVec and support for RapidIO." In that article IBM says they are talking to customers about what they want on top of AltiVec. This may assume a level of AltiVec utilization.

A very interesting IBM paper entitled, "Effect of increasing chip density on the evolution of computer architectures", by R. Nadir, of IBM, discusses in a nutshell, two different ways in which billion-transitor chips can be made in the near future, with greater performance by moving more of the entire system onto the chip. The first technique describes bringing memory closer to the processors in a symmetric multiprocessor cell (Ed. Note: sounds like IBM's mythical Cell processor which was recently announced) and the second process is the classic System-on-a-Chip approach. In this article the Power4 and PowerPC are both discussed. To read the article, download the PDF here.

It should be pointed out that Nadir's article sheds light on a trend in the processor space wherein processors today find re-use in different markets. In a series of diagrams, Nadir describes today's processors and markets: 1) embedded-PowerPC405, for embedded markets; 2) game-PowerPC Gekko, for game markets; 3) desktop-Pentium4, for desktop markets; and 4) workstation-IBM Power4, for workstations and servers. Nadir continues to describe a trajectory wherein with a single chip SMP design, there could be further consolidation and reuse. While embedded chips would utilize system on chip (SOC) designs, Game, Desktop and Workstation computers would all utilize a SMP-on-a-chip type processor.

With IBM gearing up to supply Sony with a PowerPC chip that goes beyond Moore's Law (Sony said in an article that Moore's Law is too slow) for the Playstation 3 in 2004, IBM seems to be developing at least some of its chip technologies along the lines described by Nadir. And Apple, with the new Xserve and its direct L3 cache format, moves closer to the arrangements of large onboard memory and memory controlers on the PowerPC chip itself.

More Articles on IBM PowerPC, Power4 and AltiVec

The following list of articles was consulted for this report, with some dating back to 1999.

IBM pushes to 2 GHz: http://news.com.com/2100-1001-257421.html?legacy=cnet

Motorola may integrate DRAM controller into PowerPC: http://www.eetimes.com/story/OEG20010828S0091

IBM mulls memory changes to PowerPC: http://www.electronicstimes.com/tech/news/OEG20010601S0027

IBM, Motorola write Book E on PowerPC: http://www.eetimes.com/story/OEG19990507S0003

IBM woos Apple with PowerPC "on steroids"