Now, NVIDIA has entered the same race—the race to deliver the world’s fastest and most capable processor for the personal computer. But unlike Intel and AMD, NVIDIA’s new RTX Spark Superchip runs the ARM instruction set, not the Intel-X86 instruction set, and thus joins Apple and Qualcomm (not to mention MediaTek) in the ARM architecture’s pursuit of taking over the PC landscape.

Death to Intel X86?

So, does this news mean doom for Intel X86? We have certainly discussed this possibility in great detail before in our critically received feature (see Architosh, “End of an Era: How Silicon Will Decide BIM’s Future,” 24 December 2025), first published for our Xpresso-4X newsletter readers. And we originally discussed ARM’s threat to Intel X86 in our even larger, critically received feature (see, Architosh, “Chip Technology, Geopolitics, and the CAD Industry,” 21 Jan 2022).

Key Takeaways

• NVIDIA’s RTX Spark Superchip is based on the ARM architecture and is similar to Apple’s and Qualcomm’s ARM SoCs in that it merges a CPU, GPU, and dedicated AI processing centers all on the same chip with a “unified memory” architecture that is incredibly fast.
• The RTX Spark has no benchmarks at this announcement, but company executives told Forbes editors that it will have all-day battery life and be performance competitive with anything else in the PC market.
• RTX Spark-based computers could massively disrupt sales of Intel and AMD X86-based computers, tilting the entire X86 Windows software ecosystem towards ARM. Leading PC makers will ship RTX Spark-based systems in the fall in premium laptop configurations and run Microsoft’s Prism X86 software emulator as well as support the growing ecosystem of native Windows on ARM software titles. 

But before we discuss why Intel X86 may be in real trouble now, let’s dig into the announcement and chip details further.

Jenson Huang, in his talk at Computex, Taipei, today, essentially says:

Huang goes on to say that with each generation of the new RTX Spark Superchip, there will be a new model for the laptop, the desktop, and the workstation computer. He further says in his talk that he is incredibly thrilled that 100 percent of the world’s PC market has joined Nvidia to reinvent the PC. Of course, Jensen Huang isn’t really capturing 100 percent of the PC industry to come on board and join them in reinventing the PC. Critically, Intel and AMD are not on board because the NVIDIA RTX Spark Superchip is the most existential threat to their PC chip business that they have likely ever faced.

NVIDIA and Microsoft reinvent the Windows PC for the Age of Personal AI. Introducing the NVIDIA RTX Spark Superchip for Windows ARM computers.

Historically, Nvidia relied on Intel and AMD to provide the X86 central processing units (CPUs) that acted as the brains, along with Nvidia graphics cards (GPUs), which ran graphics and specialized parallel processing tasks. Now RTX Spark represents a paradigm shift that targets the core profit engines of the legacy X86 giants through several critical competitive advantages.

RTX Spark Advantages

Namely, these advantages stem from the fact that NVIDIA is breaking the X86 Duopoly in high-end devices in the PC market. The RTX Spark Superchip running Microsoft’s Windows for ARM shatters this exclusivity. Now consumers will face a choice between RTX Spark-based systems from top-tier computer makers, including Dell, Lenovo, HP, Asus, and MSI, and X86-based systems running Intel and AMD processors. Which will they choose and why?

Computer buyers will want to choose NVIDIA’s RTX Spark-based systems for one very important advantage. The Spark Superchip is built from the ground up for what Huang calls the Native AI Agent Revolution. In other words, the leading AI chip company is going to bring its AI chip prowess to your everyday computing.

Let’s look at the NVIDIA Spark Superchip in detail. So what does it consist of?

• CPU Architecture — ARM (NVIDIA and MediaTek co-developed the design)
• CPU Core Count — 20-core (10 Cortex-X925 + 10 Cortex-A725)
• GPU Architecture — NVIDIA Blackwell (up to 6,144 CUDA cores)
• Memory System — Up to 128 GB of LPDDR5X Unified Memory
• Processor Node — TSMC-3 nanometer

The RTX Spark Superchip will fuse two chiplets: a GPU based on NVIDIA’s Blackwell architecture and a 20-core NVIDIA Grace (ARM-based) CPU. Unified memory is what the Spark Superchip has in common with ARM chips from Apple and Qualcomm, but to stand apart from them, the RTX Spark chip supports up to 128 GB of unified memory in configurations that are engineered for heavy desktop-class AI and graphics workloads rather than mobile-first efficiency. Unlike Apple and Qualcomm, the NVIDIA RTX Spark superchip includes NVIDIA’s NVLink memory bandwidth technology, yielding up to 600 GB/s. And the chip also features Blackwell CUDA cores, something that Qualcomm and Apple are locked out of, as this technology is proprietary.

MORE: ARES 2027 Deep Dive: AI, Automation and BIM-to-DWG Workflows

Even if Intel and AMD launched their own unified memory, ARM-based processors to compete with the RTX Spark, they would have to strike a licensing deal to obtain the Blackwell GPU with CUDA cores. CUDA is, indeed, NVIDIA’s strongest leverage in computing in the age of AI.

Architosh will share more on RTX Spark as we learn more details, but in our section below, we explore the industry impact of this new chip announcement. For further details, read here.

Architosh Analysis and Commentary

Early feedback from the computer industry over the NVIDIA RTX Spark Superchip is a mix of massive excitement over the hardware’s capabilities, mixed with a healthy dose of debate over its impact on the Windows X86 software ecosystem. It would be premature to rush to the conclusion that AMD and Intel cannot compete with NVIDIA in the PC market for central processing units. Much depends on the true performance advantages NVIDIA’s RTX Spark can deliver in general and AI computing. However, in general, the very fact that the Spark is out now and is ARM-based sends another powerful signal to the market that the ARM architecture is rising while the Intel X86 architecture is in decline. This begs the question about software ecosystem disruption.

How will Windows software be developed in the future? If software on Windows moves to an ARM-priority-based market, this will actually aid Apple as well, since their hardware is also ARM-based, and emulating Windows on ARM today on MacOS systems is very prevalent and performative. 

Furthermore, with NVIDIA focusing on getting Windows gaming developers and graphics app developers moved over to native ARM development for these new RTX Spark-based computers, this also shifts the tools behind the software development in a direction that will likely aid Apple as well. It will be easier for a developer to develop for ARM on both Windows and Mac since they share the same chip architecture and presumably an increasing set of ARM development tools. The question then becomes, how does the CAD industry react to all of this? What will Autodesk and SolidWorks do in response to a possible future where the world’s fastest Windows PCs are running NVIDIA RTX Spark Superchips? 

The post NVIDIA unveils RTX Spark—ARM-based Superchip for Windows PCs appeared first on Architosh.

We have seen the Fusion technology Apple has used in the past for creating the “Ultra” versions of its M1, M2, and M3 chips. It skipped the M4 Ultra to focus on re-engineering Apple Silicon for the M5 line. Apple says this is the biggest chip design update since the original M-series debuted.

In this article, we will dive into details that others may miss and highlight the relevance of these chips to the AEC markets.

M5 Pro and Max

The M5 Pro and M5 Max are interesting because now the fusion technology is deployed between the Pro and Max, whereas previously it was deployed between the Max and Ultra. More than that, the division is between CPU and GPU, where before an entire Max chip was doubled using Apple Fusion to create the Ultra version.

Apple’s M5 Pro and M5 Max introduce a totally new Apple Silicon architectural strategy and industry-leading chip performance.

This time, the CPU for the Pro and Max is essentially the same, just binned with one core each, but the GPU die is doubled to get the Max variant from the Pro.

• The M5 Pro – 
• 5/6 – super cores
• 10/12 performance cores (18 core total max)
• 16/20 GPU cores

Or the:

• M5 Max –
• 6 – super cores
• 12 – performance cores (18 cores total)
• 32/40 GPU cores

Apple explicitly says in its press release that the “M5 Max pairs the 18-core CPU with an up-to-40-core GPU.” So the CPU and GPUs are definitely their own dies, and the GPU dies come in two sizes, and Apple may have engineered them so they are cuttable at the wafer level to control how many of each-sized GPU die they need.

Fusion Architecture Details

The new Fusion Architecture connects two dies with advanced IP blocks and maintains high bandwidth and low latency using advanced packaging. Exactly which sub-components on which die isn’t fully clear.

M5 Pro chip diagram (not official), based on Apple’s descriptions of the Apple Fusion Architecture. (Image: screen grab from Gary Explains, with Architosh-added text)

To make this efficient at the wafer level, the CPU and GPU dies would likely want to be the same die size, unless Apple engineered its chiplet so that TSMC produced the CPU and GPU dies on separate wafer runs. But how Apple achieves this at the manufacturing level isn’t really our concern, and we may learn about it eventually.

Super Cores and P Cores Only

Another interesting aspect of the M5 Pro and M5 Max chips is that they feature only performance and super cores. There are no efficiency cores for the Pro and Max. This isn’t a full departure from ARM’s big.LITTLE architecture philosophy as the super cores are larger than the performance cores, but it signals that Apple is gunning to compete with chip competitors trying to nip at its heels, especially at multicore CPU performance.

MORE: End of an Era: How Silicon Will Decide BIM’s Future

For instance, ARM competitor Qualcomm, with its Oryon architecture, only has “performance” and “prime” cores and explicitly omits traditional efficiency (or E) cores. Qualcomm’s thinking is that performance cores are efficient enough at low voltages to handle background tasks without needing purpose-built efficiency cores. Apple seems to have fully embraced this strategy as well, at least for the M5 Pro and M5 Max.

The GPU also features Neural Accelerators integrated into each GPU core. This is a game-changer for GPU performance and AI performance alike, and it shows in Apple’s AI benchmarks.

Node and Performance

The M5 Pro and M5 Max are manufactured on TSMC’s third-generation 3-nm process (N3P), which yields only a 4% improvement in transistor density but up to 30% faster multithreaded CPU performance, which is notable. GPU performance is also substantially faster than the M4 series. Even without the efficiency cores, the new node is helping Apple get up to 24 hours of battery life.

Another notable improvement is the memory speed-up. Bandwidth is now up to 307GB/s for the M5 Pro and 614GB/s for the M5 Max, with maximum memory of 64GB and 128GB, respectively.

MORE: Intel Debuts Panther Lake—Intel 18A: For CAD and BIM? 

For graphics performance, the new chips feature enhanced shader cores with second-generation dynamic caching and hardware-accelerated mesh shading. Also, Apple’s third-generation ray-tracing engine is onboard these new chips, which will improve rendering performance across numerous AEC applications.

Massive Single-Core

Apple leads the world in single-core performance, and the new super cores are the world’s fastest yet. This is partly driven by increased front-end bandwidth (wider front end, new cache hierarchy, and new branch prediction technology. Apple remains hyper-focused on industry-leading IPC (instructions per clock), and the ultra-wide fetch and decoder can process more instructions simultaneously before they even reach the execution units.

Vectorworks Architect is showcased on Apple’s M5 Pro and M5 Max webpage. The application is a model of modern code development for OS-centric optimization across platforms, but especially macOS. Maxon’s Redshift rendering engine is also noted and featured in this image. These kinds of tools are highly single-threaded and dependent for main design modeling tasks.

At the same time, the 30% improvement in multicore CPU performance is also dramatic, and we will see how the M5 Max fairs against the leading Apple Silicon chip on multithreaded performance, the M3 Ultra.

AI Performance

But beyond Fusion, Apple’s strategy of placing a Neural Accelerator into every single GPU core is another major architectural change in Apple Silicon, yielding big results. Apple says the M5 Pro and M5 Max offer over 4x peak GPU compute for AI compared to the previous M4 generation of chips. This is massive.

Additionally, the Neural Engine itself is faster than previous versions, and these chips also boast the latest Media Engine for video workflows and an industry-first Memory Integrity Enforcement and Thunderbolt 5. Learn more here.

Architosh Analysis and Commentary

Apple Silicon has traditionally been strongest in IPC and single-core performance, an area we have emphasized is absolutely critical to the CAD industry because CAD and 3D software are intrinsically resistant to parallelization. The entire M5 chip family continues to place emphasis on this industry leadership, which is a boon for performance-hungry BIM and CAD professionals using macOS native CAD and BIM platforms, from AutoCAD to Vectorworks and everything in between. 

It is notable that the M5 base model chip also features the same architecture core improvements, with four Super cores being paired with six Efficiency Cores. The base M5 chip maxes out its unified memory at 32 GB, which is the threshold you need to run Windows in Parallels in a professional AEC environment. This is the one regret we have, as a 48 GB option would have given the market a more affordable machine for contractors. They only need to run tools like Revit, SketchUp, and Bluebeam, along with web-based tools like Procore, but they are generally not authoring in tools like Revit. 

For architects who need access to Windows apps like Revit but prefer working on the Mac, the MacBook Pro with M5 Pro at 48 GB is an ideal starting point for a powerful mobile workstation with industry-leading snappiness across all native applications. 

Beyond all this, the new shader cores, third-gen ray-tracing engine, and Neural Accelerators in each GPU core all benefit visualization tools and workflows that architects and designers need.

The post Apple M5 Pro and M5 Max introduce new Fusion Architecture appeared first on Architosh.

The Chips

The Intel Core Ultra Series (Panther Lake) processors deliver up to 60% better multithreaded performance and 77% faster gaming performance compared to previous generations. But the real thrust of the improvements is the energy efficiency. And this news has sent Intel’s stock surging over 6% yesterday as the company discussed the technicals of Panther Lake.

A chip die shot of Intel Core Ultra Series 3 (Panther Lake). This latest processor series delivers dramatic raw performance and power-per-watt improvements over Intel’s previous generation. They are fundamentally bringing desktop-class performance to mobile computing and are aimed at competing with ARM-class processors from Apple and Qualcomm.

In terms of products in the Core Ultra Series 3 these include:

• Core Ultra X9 388H  — The flagship processor, which is approximately 19% faster than the previous generation Core Ultra 9 285H, and is designed to compete with top-tier mobile chips from AMD, Apple, and Qualcomm.
• Core Ultra 9 386H — There are incremental gains over previous 16-core mobile models from Intel
• Core Ultra 7 365 —  Similar single-core performance to current AMD Ryzen AI 7 350
• Core Ultra 3 205 — 30% higher multicore than Core i3-14100

AI performance is at the center of the story around Panther Lake, with Intel claiming leadership performance in the Geekbench AI test suite, with the NPU chip component yielding 50 TOPS, which will allow the computer to run local AI tasks significantly faster than competing chips from AMD and Qualcomm.

Panther Lake Architecture

As we noted in our recent feature (see Architosh, “End of an Era: How Silicon Will Decide BIM’s Future,” 24 December 2025), Intel’s chip architectural strategy has increasingly followed the heterogeneous compute paradigm established by ARM architecture chip makers like Apple and Qualcomm. This means the chip is a mixture of different types of computing units and cores.

Panther Lake architecture includes new next-generation P-cores (which are your snappy and responsive experience performance cores), plus next-gen E-cores (which drive multithreaded performance and parallelism) and new LP-E cores (which focus on energy-efficient compute, like everyday tasks such as email). These cores come in a 4+8+4 configuration, delivering a total 16-core chip with very notable multicore performance improvements.

Panther Lake also features a new NPU (neural processing unit) with NPU 5 Architecture delivering up to 50 TOPS across the stack, putting Intel very near if not at the very top of AI on-chip compute. Additionally, the new Intel Core Ultra Series 3 processors can optionally contain a built-in Intel Arc GPU for advanced graphics.

This image shows the entire chip package (not just the processor itself). The new Panther Lake generation features a multi-die (chiplet) architecture with a modular Tile design. Intel uses Feveros 3D packaging to stack several specialized silicon tiles on a single base. The flagship processor, Core Ultra X9, features a much larger Intel Arc B390 GPU tile with 12 Xe3 cores, which is a 50% increase in graphics hardware over the previous generation.

Unlike the previous generation Lunar Lake, Panther Lake goes back to placing the memory on the motherboard (not integrated). Lunar Lake memory on package (MoP) chip design emulating Apple’s on-chip integrated memory, but ex-CEO Pat Gelsinger was noted as saying that direction was a mistake because it limits customer configuration flexibility. This has been noted about Apple’s M-series as well, and is one of the few remaining reasons against Apple targeting workstation computing markets more successfully, where memory far above 128GB is now possible.

The Ultra X9, Ultra 9, and Ultra 7 (Panther Lake) can have a maximum memory of 96 GB (LPDDR5x) or 128 GB (DDR5). This far exceeds 48 GB of unified memory in Apple’s flagship MacBook Pro.

Battery Power

Panther Lake was designed with PowerVie technology, which is specifically aimed at addressing the “performance cliff” that was common to older x86 laptops when unplugged. This is an area where Intel and AMD have an uphill battle with Apple Silicon, which is designed to deliver an identical performance whether unplugged or plugged. Still, Panther Lake is specifically designed to narrow this performance gap and also deliver much longer battery life, up to 27 hours, says Intel.

Thanks to Intel PowerVie’s backside power delivery architecture, Panther Lake reduces IR (voltage) drop, allowing the chip to sustain higher clock speeds at lower voltages, eliminating (mostly) the need to cycle down clocks to conserve power when unplugged. It still cycles down, but just not as aggressively as previous Intel chips did.

Just like Apple, Intel Panther Lake uses a “low power island” for background tasks, which means the high-performance (and energy-consuming) performance cores (P-cores) stay dormant until they are truly needed. Apparently, this will help Panther Lake be “bursty” even on battery, like Apple Silicon can. As we discussed at length in our feature on silicon and BIM, “burstyness” is a standard feature of CAD, BIM, and 3D modeling applications. So bursty performance means “snappy” application interactions.

The 60% percent improvement when working in multithreaded workloads is a very meaningful improvement profesional users in a range of industries.

For more information, visit here.

Architosh Analysis and Commentary

Panther Lake for CAD and 3D Pros

While Intel is a long way off from regaining the single-core performance crown from Apple—and we know how much CAD and BIM work is necessarily single-threaded—these new chips offer CAD professionals a big boost over previous-generation equipment. And the Intel Core Ultra X9 (the flagship Panther Lake chip) essentially matches Apple’s latest M5 in Geekbench 6.5 multicore scores (17,687 ±  versus 17,862 ± / Intel to Apple). 

This means that when working in CPU-generated rendered viewports, the multicore performance of that rendering work should be roughly equal. However, when moving around, doing modeling, model reconstruction, model manipulation, and general UI responsiveness, single-threaded speed is king. And from that vantage point, Intel has more work cut out for itself if it wants to catch up to Apple. 

Other benefits for CAD pros include sustained performance with PowerVie when untethered. Then there is the graphics with Panther Lake’s Intel Xe3 integrated GPU tech. A reported 3DMark Time Spy test shows the Core Ultra X9 (Xe3) scoring 6,300 versus an estimated translation of 4,800 for the M5. This score of 6,300 is a landmark for a mobile PC processor and surpasses the average score of a mobile Nvidia RTX 3050. As we noted in our recent review of the Intel Arc Pro B50 GPU for workstations, Intel has some real chops to display, with the Intel Arc PRO B50 outperforming the comparable Nvidia RTX A1000 in performance per dollar (Geekbench 6 GPU/USD).

The bottom line is that Panther Lake looks to be a big success (and also a redeeming manufacturing success for Intel) and will lead to many new thin, lightweight professional laptops that pro users on Windows will certainly enjoy. With battery life supposedly up to 27 hours, this chip should greatly boost unthethered CAD/BIM industry performance in the field. 

The post Intel debuts Panther Lake—Intel 18A: For CAD and BIM? appeared first on Architosh.

‘End of an Era: How Silicon Will Decide BIM’s Future’ was first published on 18 December 2025 inside our Xpresso-4X newsletter. To gain early access to some of our best content, subscribe to Xpresso-4X now. It’s free! 

FOR YEARS, THE AEC INDUSTRY HAS FRAMED THE FUTURE OF BIM as a software problem. Faster tools. Smarter automation. Better collaboration. But beneath every roadmap, every keynote, and every feature release lies a deeper force shaping what is—and isn’t—possible.

That force is silicon.

The next phase of BIM—and AEC software technologies as a whole—will not be decided by interface changes or subscription and software delivery models alone. It will be decided by the physics of modern semiconductors and the architectural assumptions embedded in the tools that architects and designers rely on every day.

The Assumptions CAD and BIM Were Built On

In our last major special feature on the CAD industry and semiconductors (see: Architosh, “Chip Technology, Geopolitics, and the CAD Industry,” 21 Jan 2022), we laid out some of the emerging changes shaping the semiconductor space, especially the rise of ARM processors. This time, we go deeper into the facts, trends, and stories shaping that change and the impacts on the CAD and BIM industry.

For more than two decades, professional design software has evolved within a remarkably stable computing environment. Revit ran on Windows. Windows ran on Intel x86 processors. And each new generation of CPUs delivered higher clock speeds and better single-thread performance.

Those assumptions shaped everything from geometry kernels and solvers to regeneration logic and viewport behavior. Performance gains arrived reliably, year after year, with little need to rethink fundamental software architecture.^{1 2 3} 

That era has ended.

The inflection point arrived quietly between 2015 and 2019, when Intel’s long-promised 10nm manufacturing process failed to arrive on schedule. What appeared at first to be a temporary execution problem was, in fact, the first visible sign of a structural shift in how computing performance would scale going forward.⁴

When x86 Met Physics (High-Frequency Era)

Intel’s 10nm struggle wasn’t just about delays. It was a collision between decades-old architectural assumptions and the physical limits of advanced semiconductor manufacturing.⁵

To understand what happened at Intel—and why BIM is now entering a new computing era—we need to briefly visit the transistor level. (see image below or click here for a fun basic physical model explanation, or here for a complete visual history of Intel’s transistors, or here for a far more detailed and illustrated history of the transistor over time. All of those links are videos.)

SIDEBAR — How a Transistor Works. A transistor consists of a channel for electrical current, a source and drain on either end, and a gate that controls whether current flows through the channel (under the gate). A voltage at the gate creates an electric field that opens or closes the channel (in grey color above), switching digital “0’s” or “1’s”. Billions of these switches (transistors) toggle on and off billions of times per second, in modern semiconductors. To understand this more completely, watch any of the three video references listed above this graphic.

For 40 years, Intel mastered the art of shrinking these switches. Moore’s Law wasn’t just a prediction — it was Intel’s operational rhythm. Each new node promised more transistors, higher frequency, and therefore higher performance. ^{4 6 7}

x86 especially thrived in this model. Its architectural assumptions were tied to:

• very deep pipelines (15-20+ stages)
• high clock frequencies (4.0 – 6 GHz turbo boosts)
• complex variable-length instruction decoding
• massive out-of-order execution windows
• significant speculative-execution chip design

In the High-Frequency Era, this design delivered extraordinary single-thread performance—the exact metric for which tools like Revit were optimized.^{2 3}  In fact, most CAD and BIM users likely don’t know that CAD tools and 3D geometry engines, by their logical nature, aren’t viable candidates for multi-threaded coding and therefore multi-core chip acceleration. Instead, their speed depends mostly on super-fast single-core performance, and users would leverage faster workstations and computers by acquiring x86 CPUs with faster frequencies (measured in GHz).^{2 3 4}

However, by the mid-2010s, several forces converged at advanced nodes. At smaller nodes, transistors face hard constraints: reduced voltage headroom, increased leakage, higher wire resistance, and tighter timing margins. Intel’s x86 designs—optimized for deep pipelines and very high clock speeds—depend on stable voltage and precise timing across complex execution paths.^{5 8 9 10 13} 

SIDEBAR — How a Transistor Works: By the time Intel ran into problems at 10nm, the semiconductor industry had long moved to FinFET transistors. Instead of lying flat, the channel was rotated 90 degrees. This enabled the gate to wrap around the channel on three sides, thereby providing greater control over the source-to-drain current. These vertical channels offered another benefit: more of them could be stuffed into the shrinking real estate of microprocessors. But importantly, the metal interconnects for power and signal in chips are now getting impossibly close to each other and creating numerous electrical issues.

At 10nm, those requirements became increasingly difficult to satisfy. Metal interconnects grew so small that resistance rose sharply. Multi-patterned lithography introduced variability and yield problems. Timing closure became a challenge not just for experimental designs, but for mainstream high-frequency CPUs.⁹

For the first time in history, Intel’s new node produced chips that ran slower at dramatically lower frequencies and with poor performance compared to 10nm goals.

The company’s decision to fabricate these impossibly fine features using complex multi-patterned DUV lithography (rather than the emerging EUV) led to staggering defect rates and yield issues. It wasn’t that Intel forgot how to manufacture chips — it was that x86’s architectural demands ran headlong into fundamental semiconductor manufacturing physical limits.^{11 12} 

This was the moment the industry should have realized: the performance ladder Revit and other professional software had been climbing for two decades was breaking down. And the implications went far beyond Intel’s roadmap and the CAD and BIM software industry.

They signaled the end of the High-Frequency Era that professional software had grown accustomed to.

The Voltage-Limited Era Arrives

As transistor scaling continued, the industry crossed an invisible threshold. Voltage—rather than frequency—became the dominant limiting factor. Power density, heat dissipation, and energy efficiency emerged as first-order constraints.^{14 15 16} 

While Intel struggled, a different architecture— ARM—was quietly scaling in a direction better aligned with modern transistor physics.

A picture of the Amazon Graviton4 CPU. (Image: Amazon). Amazon has aggressively deployed its ARM-based Graviton series processors over x86 due to the lowered total cost of ownership. From the beginning, they offered substantially superior power performance per watt.

ARM was designed from the beginning for low-voltage, fixed-length instructions and high IPC (instructions per cycle). It never needed 5 GHz turbo modes or 20-stage pipelines. Its efficiency model was a better match for the emerging transistor world, one where performance per watt would displace the metric of just pure performance.

ARM thrives on:

• shallow pipelines
• simpler decode paths
• wide, power-efficient execution
• low-voltage operation
• excellent thermal behavior
• massive parallelism

As nodes shrink toward—and below—2nm, voltage becomes the hard limit. Frequency is no longer the performance driver. Performance per watt is the new dominant metric.^{15 16}

What once made ARM ideal for mobile devices now makes it well-suited to modern semiconductor nodes. The Voltage-Limited Era.

Apple Silicon Changed the Conversation

When Apple introduced the M1 in 2020, it did more than launch a new processor family. It demonstrated that ARM-based CPUs could outperform x86 designs in both performance and efficiency within mainstream professional workloads.²⁰

Apple’s success was often attributed to vertical integration or unified memory. Those factors mattered—but the deeper reason was architectural alignment with modern silicon physics.

Apple’s M1 “Apple Silicon” changed the entire trajectory of the PC industry when it was introduced in the fall of 2020, demonstrating breathtaking performance-per-watt advantages over both Intel and AMD. Analysts said at the time Apple deployed unique SoC advantages like its unified memory architecture, and thus downplayed the benefits of the ARM architecture itself. Qualcomm would later introduce equally stunning new Snapdragon X Elite chips without many of the same advantages Apple Silicon had. (see below).

Apple’s cores achieved high single-thread performance at relatively modest clock speeds, proving that the performance model long associated with x86 was no longer the only path forward.

In a world where voltage limits mattered, Apple’s architectural strategy was better aligned with the physics of semiconductor manufacturing ^{18 19 20} 

Qualcomm Proved It Wasn’t Just Apple

Without Apple’s vertical integration or unified memory advantage, Qualcomm’s ARM-based Snapdragon X Elite still matched or beat Intel and AMD on:

• IPC
• sustained performance
• power efficiency
• bursty (CAD/BIM) productivity workloads

The Hyperscalers Follow the Physics

Intel’s Countermove: 18A and Backside Power Delivery

In RibbonFET, the “fins” of FinFET process technology are laid on their sides and then spaced vertically. They thus look like “ribbons” in the image above (Intel). The transistor “gate” is the silver block that the ribbons (silicon channels) pass through. Voltage applied to the gate either allows or prevents current from passing through the channel, resulting in a “0” or “1” at the transistor.

These are very meaningful advances. They will help Intel remain competitive. And both Intel and AMD have long ago altered their chip architectures to capitalize on the efficiencies of RISC (Reduced Instruction Set Computing) based chip design. Today’s modern x86 processors are actually a hybrid of CISC (Common Instruction Set Computing) and an ARM-like RISC design, with the remaining but unavoidable legacy baggage of x86 variable-length instructions and CISC-to-RISC conversion layers.²⁹

Despite all this engineering and the backside power delivery (BSPDN) and gate-all-around transistors (GAA-FinFET), the underlying physics that limit x86’s deep pipelines and demand for high frequencies don’t go away. The architectural characteristics that favor ARM—low voltage operation, efficient execution, and heterogeneous integration—remain better aligned with the long-term direction of semiconductor physics.

PowerVia is Intel’s tradename for backside power delivery. (Image: Intel). This is a 3D section through a chip, which is made up of many layers. 18A innovates by separating power and signal wiring layers, thereby improving voltage stability and resolving numerous power- and current-related issues.

Intel may jump ahead at the “leading edge” chip manufacturing node. Intel will no doubt remain competitive over the next few years. It may even lead again in specific segments. But the long arc of semiconductor physics now bends away from x86.^{27 28 30}

And Intel knows this.

AMD and Intel are rumored to have secret ARM chip designs in the works—plans they will never make public until they truly see themselves as having no choice but to stay competitive with ARM-based chips.³¹

Intel even has a fast-growing partnership with SoftBank, with the Japanese firm owning 2% of Intel. Why would ARM’s majority owner partner with its leading x86 chip rival?³²

What This Means for BIM and CAD

An industry shift from x86 to ARM is already underway, thanks to Microsoft’s robust push in that direction.³⁴  But the process is a decade-long affair. The implications for legacy software stacks are massive. And no category is more exposed to this challenge than CAD and BIM.

Revit, Rhino, SolidWorks, and Maya were built during the peak of x86’s High-Frequency Era. Their engines, geometry kernels, solvers, and memory patterns all assume:

• a single-thread performance ceiling that keeps rising
• desktop tower thermals
• CPU-centric computation
• a predictable increase in clock speed

However, all of those assumptions are collapsing if not already collapsed.

Performance gains now come from parallelism, memory bandwidth, accelerators, and heterogeneous compute—not just from higher GHz. Software that depends heavily on single-thread CPU performance faces diminishing returns on legacy platforms.

At the same time, the market is already shifting:

• Core geometry kernels now support ARM natively.³⁵
• BIM and CAD applications ship ARM-optimized versions for macOS and, soon, Windows on ARM.
• Designers increasingly work on ARM-based laptops, tablets, and cloud workstations.
• AI-driven workflows rely on GPUs and NPUs as much as CPUs.

The shift is no longer hypothetical. It is underway. To be sure, many of the biggest x86-based CAD and BIM apps are severely tied down to legacy code and dependencies. But competitors move quickly. And since the computing paradigm shift from the desktop era to the mobile-cloud-first era, the BIM industry, in particular, is facing the rise of well-funded BIM 2.0 startups attacking long-standing pain points.

The question is no longer whether BIM will move to ARM, but when exactly and who will be left behind when it does.

Heterogeneous Compute: GPU Geometry, AI Inference, Hybrid Evaluation

When it comes to the hybrid future of compute, ARM has led the industry since it was created specifically for power efficiency and embedded systems, where heterogeneity has long been the norm.³⁶

Additionally, since Dennard scaling ran out of runway—the scaling law that was crucial to the single-core performance of the x86 architecture—parallelization and multi-threading were seen as critical to future semiconductor performance gains.^{37 38 39}

The future of BIM will rely much less on single-core CPU-centric execution and much more on heterogeneous compute, where CPUs, GPUs, NPUs, and dedicated accelerators each handle different parts of the workload.^{40 41}

Future BIM systems will depend on:

• GPU-based generative AI modeling
• AI-assisted constraint solving
• AI-driven modeling assistance
• GPU and NPU shape inference
• hybrid CPU-GPU-AI simulation/model evaluation
• GPU or NPU-driven AI training on proprietary data
• mixed CPU/GPU/NPU pipelines
• massive memory bandwidth
• low-latency parallel workloads

These compute examples encompass much of what was shown to attendees at Autodesk University 2025 this past fall, with the introduction of Autodesk’s Neural CAD engines. ⁴¹

Even leading geometry engines are investigating GPU acceleration, but less on the core geometric modeling kernel and more on simulation (CFD on GPU), visualization, and AI. But the big game changers are generative AI and inference modeling workflows for the BIM (AEC) market.

MORE: AU25: All About Autodesk’s AI Neural CAD Engines

In the architectural industry, new AI software technologies will leverage the features of heterogeneous chip architectures—especially those with larger on-chip fast memory (like Apple’s unified memory or AMD’s recent AMD processors with enough onboard memory to load smaller LLMs for proprietary firm data.

Image of Autodesk’s geometry-oriented AI foundation model, or Neural CAD Engine, where AI inference can generatively shape 3D model data. (Architosh)

While traditional geometric kernels (think Spatial or Parasolid) struggle to parallelize modeling operations, AI “model inference” can generate, test, predict, and evaluate options in parallel, working with both open data and proprietary firm data stored “on-chip” or in the cloud. At the same time, heterogeneous chips can do “on-device” AI training on large sets of firm data (previous building designs and their metadata).

All of this shifts future BIM workflows from entirely CPU-bound (sans rendering and viewport generation) to a heterogeneous mix of GPU and NPU AI compute streams, addressing matters like:

• spatial “test-fit” model generation
• “KPI-driven” iteration
• clash detection, object clearance evaluation checks
• building, energy code compliance checks/optimization
• building energy and carbon analysis checks/optimization
• building simulations/optimization

This will change not just standard architectural workflows, but the physics of how BIM performance scales at the silicon level. Massive building and infrastructure projects may not scale onto “on-chip” memory and may need transport between on-chip memory and system storage memory. At AU25, the folks at a leading workstation maker emphasized this point in discussing AMD’s latest AI chip, which is fundamentally far more heterogeneous than past designs.

Image of Autodesk’s AI foundation model, or Neural CAD Engine, powering a version of Autodesk Forma where AI inference can generatively shape and test-fit 3D building model data. (Architosh). Additionally, AI software could “train” on existing BIM model data of a more proprietary nature, in which case, sensitive company IP may prefer that data to sit in on-chip memory and be handled by on-device or on-prem AI compute rather than through public cloud compute.

The important fact about the rise of heterogeneous compute is this. In the future of BIM, the CPU is no longer the only star. It is part of an ensemble cast.

The Future of BIM: The Silicon Will Decide

The future of BIM will not be shaped by nostalgia or incumbency. It will be determined by which computing platforms scale best within the constraints of modern silicon.

The High-Frequency Era is over. The Voltage-Limited Era has arrived.

In this new environment, Intel’s x86 architecture has lost its automatic advantage. Hyperscalers have moved past it, prioritizing performance per watt over raw clock speed. Even Microsoft—the other half of the Wintel duopoly—has embraced ARM, developing its own ARM-based datacenter processors and aggressively advancing Windows on ARM through its partnership with Qualcomm following its acquisition of Nuvia.

Qualcomm’s Snapdragon X Elite made clear that ARM’s advantages are not confined to the cloud. Its Oryon cores deliver exceptional IPC and industry-leading performance per watt, validating ARM’s relevance across both datacenter and client computing.

Legendary chip architect Jim Keller has noted that, at the instruction-set level, ARM’s efficiency advantage over x86 may be as little as 5%.⁴² That assessment matters. It suggests x86’s inherent disadvantages in the new voltage-limited era are often overstated. Moreover, x86 chip makers (Intel and AMD have been rapidly moving in the ARM-like direction to address heterogeneous computing and today’s emphasis on performance per watt. AMD’s new Ryzen AI Max Pro series chips emulate Apple’s M-series SoCs by integrating CPU, GPU, and NPU cores on a single die, with a unified memory architecture that allows all cores to access a single, large pool of system memory. (see: YahooTech, “AMD’s New Ryzen AI Max CPUs are Built for MacBook Pro Competitors,” 6 Jan 2025).

x86 is not fundamentally broken—and Intel and AMD’s engineering prowess should never be dismissed. But momentum matters. And the momentum continues toward ARM, not away from it. As further evidence, we can note SoftBank’s acquisition of Ampere Computing this year for USD 6.5 billion. Ampere makes ARM chips for the datacenter and counts Oracle as a major client. Both SoftBank and Oracle are key players in the USD 500 billion AI datacenter project known as Stargate.

x86’s dominance in the datacenter hasn’t disappeared entirely; just the assumptions that led to it.

In a similar way, the assumptions that led to x86 dominance in PCs have largely disappeared or changed. The challenging part is always the software ecosystems that need conversion. And this is where x86 holds a major advantage over ARM: software compatibility requires a commitment. At first, the progress is slow, but it builds quietly and then quickly.

Going forward, the physics point decisively in ARM’s direction.

For BIM and CAD industries built on x86-era assumptions, the mandate is clear:

Adapt—or risk being disrupted.

End Notes

For those who are interested in diving deeper into this article’s facts, claims, and arguments, we have over 42 annotated footnotes for this article, representing weeks’ worth of research and reading. These notes are available as a companion special feature on Architosh titled: “INSIDER Only: How Silicon Will Decide BIM’s Future — Footnotes.”

The article is exclusively available to our many Architosh INSIDER Member subscribers.

The post End of an Era: How Silicon Will Decide BIM’s Future appeared first on Architosh.

The article, however, will debut first this week in the next Xpresso-4X newsletter arriving this Thursday, 18 December 2025. [Editor’s note: This article is now live]

Why Silicon Decides

The features excerpt reads:

“As computing enters the voltage-limited era, the shift away from x86 toward ARM—already reshaping datacenters, laptops, and cloud platforms—carries consequences for architectural computing. This feature explores how those silicon realities are redefining BIM’s future, and why adaptation is no longer an option.”

It is important to note that the notion that silicon drives software, not the other way around, is not new. It has largely always been the case.

As microprocessors gain transistors and computational performance, roughly every 10x improvement, a new type of computer (or computing era) emerges, with periods of overlap.

At every 10x leap in microprocessor power (performance), a new type of computing has emerged. If we look at this chart, we are now in the era of AI Compute. In the latter half of the first decade, we were in the era of smartphone and tablet compute (cellular devices) and smoothly entered the era of cloud compute (datacenter). Yet, today’s dominant BIM and CAD solutions were all architected during the Workstation and Desktop eras.

Yet, the tools we use today in CAD and BIM industries are originally from the Workstation and Desktop eras. Today’s BIM 2.0 solutions are challenging desktop-era tools by leveraging unique capabilities enabled by the cloud (datacenter) compute paradigm.

But the AI computer era is different. It is categorically scaling (innovation, investment, and speculation) at unprecedented speeds, not seen since the Dot-Com boom. Because of this scale, it is placing unprecedented emphasis on energy efficiency due to its exponential electricity use.

Heterogeneous Silicon

Mobility has been around for decades, but smartphones and tablets have exponentially increased the number of mobile computer devices. As a result, ARM processors today outnumber x86 processors by nearly 30:1. And ARM chips were designed from the beginning with heterogeneous compute in mind, including the big.LITTLE architectural paradigm, whereas x86 chips from Intel and AMD have been playing catch-up with ARM.

In the early PC era, Intel x86 chips outnumbered RISC processors from companies like Sun Microsystems, HP, IBM, and others by a ratio very similar to 30:1. The vast volume helped Intel at both economies of scale and Wright’s Law (net positive effects from experience gained from production). Now the shoe is on the other foot, and it is AMD and Intel that are battling those same benefits now accruing to ARM and its many licensees.

Neural CAD Engines

While x86 chips have fallen behind Apple and Qualcomm badly in performance per watt (and absolute performance in cases like single-core), AMD and Intel are formidable chip design powerhouses. Yet, the battle now becomes substantially more complex in the AI era, where system-on-a-chip (SoC) designs offer key benefits such as unified system memory and high throughput between CPU, GPU, and NPU (neural) cores. Intel and AMD are emulating these designs.

This view of the geometry-oriented AI Foundational Model (neural CAD engine) can create designs spontaneously from a text prompt. It is an entirely new machine learning approach to generating CAD objects, in contrast to classical parametric CAD engines that have been in use for 40 years.

Meanwhile, the CAD and BIM industry is increasingly leveraging NPUs and GPUs for new types of workloads based on AI inference and training. Autodesk’s Neural CAD engines were shown at AU25 in Nashville this past fall.

The special feature will cover in detail how Intel ran into physics at 10nm back in the middle of the last decade and how x86 contributes to the physics problem. It also highlights how Intel’s new 18A process node dramatically attacks these physics problems and why Intel may actually potentially lead again in some performance areas.

Viewers can read the special feature on Architosh on December 24th, or earlier by signing up for the Xpresso-4X newsletter. The newsletter goes out this week on Thursday, so sign up now to not miss out.

The post Preview: End of an Era: How Silicon Will Decide BIM’s Future appeared first on Architosh.